This invention relates to error detection and correction codes.
Such codes are useful, for example, in detecting and correcting bit errors in data words stored in memory chips.
Aichelmenn, Jr., U.S. Pat. No. 4,617,664, discusses an error correction code in which the 32 bits of each data word are stored as four eight-bit bytes on eight four-bit memory chips. The first bits of all four bytes are stored in one memory chip; the second bits of all four bytes in a second memory chip; and so on. Four parity bits and four check bits are derived from the data word using a generator matrix. Each parity bit applies to one byte of the data word. Each check bit is based on a predetermined combination of bits from all of the data bytes. Later, when the possibly corrupted data word is retrieved, new parity bits and check bits are derived (using the same generator matrix) and a syndrome is formed whose bits indicate the bit positions in which the original parity and check bits differ from the new parity and check bits. Each parity syndrome bit indicates whether an error exists in the corresponding data byte. The parity syndrome bits and the check syndrome bits together may indicate (in accordance with a table) which data bits need to be corrected. Aichelman's code can correct some three bit errors and some four bit errors appearing in any one of the four-bit data chips, and can detect other bit errors.
In general, multiple bit errors in a data word are more likely to occur on a single memory chip than on different memory chips. For example if four errors occur in a single data word it is highly likely that they will occur on a single failed chip.